Semiconductor Engineering

Shift Left In DFT Design

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
Semiconductor Engineering

Smart DFT Infrastructure And Automation Are Key To Managing Design Scaling

This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable ...
EDN

DFT Analyzer Validates Design-For-Test Features

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...